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Solution
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Workaround
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Wed, 22 Jul 2026 04:15:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| Title | Output Mismatch in openRISC OR1200 CPU Leads to Unexpected Behavior |
Mon, 20 Jul 2026 19:30:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| Weaknesses | CWE-116 | |
| Metrics |
cvssV3_1
|
Fri, 17 Jul 2026 22:15:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| First Time appeared |
Openrisc
Openrisc or1200 |
|
| Vendors & Products |
Openrisc
Openrisc or1200 |
Fri, 17 Jul 2026 20:00:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| Description | An issue was discovered in openRISC OR1200 commit 83ac6b. An output mismatch between the RTL and the netlist of the or1200 cpu output port can lead to unexpected behavior. | |
| References |
|
Projects
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Status: PUBLISHED
Assigner: mitre
Published:
Updated: 2026-07-20T18:14:01.358Z
Reserved: 2025-06-16T00:00:00.000Z
Link: CVE-2025-51677
Updated: 2026-07-20T18:13:41.910Z
No data.
No data.
OpenCVE Enrichment
Updated: 2026-07-22T04:00:04Z